Tutorial 1:  Step-by-Step Guide to Designing a Low Noise Amplifier for the ISM Band (2400MHz To 2500MHz)

1.3.4 Device Model Selection

The BFU730F supplier NXP has provided two device models: MEX and SPICE. There are two ways to select a suitable or most accurate device model. Those are comparing the impedance with the s-parameter data and the IV curve with the datasheet.

ADS template simulation is used to plot the IV curve. It can be launched by clicking DesignGuide à Amplifier à DC and Bias Point Simulations and à BJT I-V Curves, Class A Power, Eff., Load, Gm vs. Bias.

1.3.4.1 Compare the impedance with the s-parameters 

Another way to select a device model is by comparing the simulation results of ADS models. Figure 1.5 shows the impedance simulation setup of s-parameter data.

Figure 1.5: S-parameter data impedance simulation

Figure 1.6 shows the MEX model impedance simulation setup. Figure 1.7 shows the correlation between MEX model simulation and S-parameter data simulation. The MEX model correlates well with s-parameter data.

Figure 1.6: MEX model impedance simulation

Figure 1.7: S11 and S12 of the MEX model compared to S-parameter data

Figure 1.8: S21 and S22 of the MEX model compared to S-parameter data

Figure 1.9 shows the SPICE model impedance simulation setup. Figure 1.10 shows the correlation between the SPICE model simulation and S-parameter data simulation. The SPICE model correlates well with s-parameter data.

Figure 1.9: SPICE model impedance simulation

Figure 1.10: S11 and S12 of the SPICE model compared to S-parameter data

Figure 1.11: S21 and S22 of the SPICE model compared to S-parameter data

The MEX model is proven as the most accurate model for BFU730F. All the simulations in the following steps will use the BFU730F MEX model.

1.3.4.2 Compare the IV curve with the datasheet 

Apart from the above-mentioned method, the DC Curve (Ic vs. Vce) can be used to select the most accurate device model. The Ic vs. Vce from the datasheet can be compared with the Ic vs. Vce plot of the MEX and SPICE model to choose the model which closely matches the datasheet.

Figure 1.12: Datasheet Ic vs Vce

Figure 1.13: MEX model Ic vs Vce

Figure 1.14: SPICE model Ic vs. Vce

After comparing Figure 1.12 with 1.13 and 1.14, the MEX model is closely matched to the datasheet.

1.4 Step 2: Obtain the LNA impedances

The next step is to obtain the LNA input and output impedances. For PA, load-pull simulation is necessary because it’s a large signal circuit. However, we can live with S-parameter simulation for LNA because of the small signal characteristics.

The template for LNA impedance extraction simulation can be found under DesignGuide à Amplifier à S-parameter Simulations. The template’s name is “S-param., Noise Fig., Gain, Stability, Circles, and Group delay versus Frequency”, as shown in Figure 1.15. S-parameter data or the MEX model can be used for the impedance simulation. I have used the MEX model, as shown in Figure 1.16.

Figure 1.15: “Noise Fig., Gain, Stability, Circles, and Group delay versus Frequency” Simulation Template

We built the biasing circuit, which gives appropriate collector-emitter voltage (Vce) and base current (I_b) according to the biasing condition of interest. The optimization setup shown on the left is done to obtain unconditional stability by optimizing RF choke, L3, and L4 and decoupling capacitors C10, C9, C11, and C12. Since these parameters are inadequate to provide unconditional stability to the LNA, we have used additional components, R7. The resistor R7 is used at the output match to trade gain for stability. With R7, we have obtained unconditional stability over a wide range of frequencies.

Figure 1.16: LNA impedances extraction schematic

In this Figure 1.17, we can move this RF Frequency selector marker to an appropriate frequency point, and all the boxes below show the parameters for the frequency point. We have set the frequency point at the center of our band of interest, 2.45GHz. The four boxes below the RF frequency selector show the s-parameter data.

We have two options here. The 1^st one is to do matching for gain. If we select this option, we need to use these impedances to do impedance matching for our LNA, and we will get the highest gain of 22 dB.

The 2^nd option is to do impedance matching for the noise figure. If we do impedance matching for our LNA using the impedances shown in the box below, we will achieve the best possible noise figure of 0.69dB. The gain is also more than 20dB, as shown in Figure 1.17. Since it will be able to meet both noise figure and gain specification, we will choose to match for noise figure, and impedances will follow as in this box.

Figure 1.17: The LNA input and output impedances

1.5 Step 3: Impedance matching

After obtaining the impedances, we have to match the input and output impedance with 50 ohms. Impedance matching is done from LNA input and output impedance to 50 ohms. The impedance we obtained from the previous simulation is the complex conjugate LNA impedance. Its shown in figure 1.18 as Zi* and Zo*. Due to this, we need to reverse the sign of the imaginary part of these impedances to get the actual LNA impedances.

Figure 1.18: The LNA impedances matching

Zo* – complex conjugate of output impedance

Zi*  – complex conjugate of input impedance

Zo  – Transistor output impedance

Zi   – Transistor input impedance

Figure 1.19 shows the output impedance matching, whereas Figure 1.20 shows the input impedance matching of the LNA. Impedance matching is done using the Smith chart utility.

The next step is to do impedance matching. ADS has a brilliant impedance-matching tool called the Smith chart utility. We will be using this tool to do impedance matching.

The 1^st step is to make sure the frequency is set to the center frequency of our band of interest and the characteristic impedance is set to 50 ohms. The next step is to insert the Q circle value. For our frequency band of interest, the calculated Q circle value is 8.

Next, we have to match the LNA output impedance to 50 ohms.

Figure 1.19: Input impedances matching using Smith chart utility

Figure 1.20: Output impedances matching using smith chart utility

Impedance matching is accomplished for load and source impedance.

1.6 Step 4: Circuit Simulation

The next step is circuit simulation. Before we simulate, we need to build the circuit. Our LNA circuit is shown in Figure 1.21. The matching component values obtained from step 3 will be used in the schematic here. On top of that, the LNA circuit also contains biasing circuit. The biasing circuit provides the required collector-emitter voltage (Vce) and base-emitter current (Ibe). We also have decoupling capacitors to filter out noise in the DC path. RF Chokes will block the RF from entering the DC path. I have incorporated DC-blocking capacitors in the Input and output matching components to block the DC from entering the RF path. All these components are shown in Figure 1.21.

Figure 1.21: LNA Circuit

Let’s move on to check our circuit simulation results. I create this data display server template. You can create a custom template like this and copy and paste it easily to recreate them, which saves a lot of time.

The s-parameter performance of the circuit simulation is shown in Figure 1.22. The LNA meets all the specifications, including gain and isolation and input and output return loss. The gain is more than 20dB which is excellent. The isolation is -29dB. The input return loss is less than -18dB, and the output return loss is less than -14.9 dB.

Figure 1.22: LNA s-parameter simulation results

Figure 1.23 shows Noise Figure and DC simulation. The excellent noise figure of 0.92dB to 0.95dB was obtained across the 2.4GHz to 2.5GHz frequency range. The Collector current (I_ce) of 0.017mA is obtained, which is also the total current draw of the LNA. The base current (Ibe) is very small and negligible, but ADS allows you to plot this as well.

Figure 1.24 shows the small signal stability analysis. Through the WS Probe, we have plotted the “Real Part of Driving Point Admittance” and “Bilateral (True Return Ratio) Loop Gain”. We also plotted µ_source & µ_load. The µ_source & µ_load > 1 across 1kHz to 20GHz shows the LNA is unconditionally stable. Moreover, the “Real Part of Driving Point Admittance” is more than zero, and the “Bilateral (True Return Ratio) Loop Gain” is less than 0 validates the mentioned conclusion.

Figure 1.23: Noise Figure and DC simulation results

Figure 1.24: LNA small signal stability analysis

Figure 1.25 shows the LNA IP3 measurement setup. Two signals with an appropriate gap will be injected into our DUT or LNA, and the output will be monitored by a spectrum analyzer. In our case, we are injecting 2.449GHz and 2.451GHz together, and the fundamental frequency is 2.45GHz and a gap of 1MHz. In the industry, sometimes this gap can be in kHz, depending upon the radio specification. The power level is -40dBm. The OIP3 can be calculated using this IP3out component in ADS. I have inserted two components because we have upper and lower-side OIP3 products.

Figure 1.25: LNA IP3 measurement setup

We will do an IP3 simulation with the EM simulation model later.

For circuit simulation, we have met all the design goals set for the s-parameter, noise figure, and stability simulations.

1.7 Step 5: Layout Design

LNA layout must be carefully designed to minimize parasitic capacitance and parasitic inductance. The layout causes parasitic capacitance and parasitic inductance. As you already know, parasitic capacitance and inductance are unwanted elements due to the nature of the PCB.

Let’s understand what causes parasitic capacitance. Figure 1.26 shows parasitic capacitance formation in a PCB. In case one, the electric field between the traces on layer one forms parasitic capacitance. In other words, the electric field created between these M2 traces in blue causes parasitic capacitance.

In case two, the electric field between a trace on layer one and metal on the neighboring layers forms parasitic capacitance. for example, the electric field formed between M2, M3, and M1 will also create parasitic capacitance.

Figure 1.26: Parasitic capacitance formation in the PCB.

Now let’s understand how parasitic inductance is formed. The magnetic field between two ends of a trace forms parasitic inductance, as shown in Figure 1.3. long traces will have huge parasitics inductance and wise versa.

Figure 1.27: Parasitic inductance formation in the PCB.

RF engineers need to be aware of the parasitic capacitance and inductance and learn to minimize or control parasitics in the layout to avoid unwanted issues such as LNA low gain or stability issues. Layout design needs to be done carefully with complete awareness of parasitics. PCB layout is designed to minimize parasitic capacitance and parasitic inductance.

Figure 1.28: Parasitic inductance formation in the PCB.

1.8 Step 6: Layout Simulation

The sixth step is to do a layout simulation. Layout simulation needs to be done after designing the layout to ensure layout parasitics are not degrading the circuit performances such as gain, noise figure, stability, IP3, etc. Our youtube videos have a step-by-step guide on importing the layout into Keysight ADS in ODB++ format, setup the EM simulation, and Running it. Please check the videos on Innowave’s youtube channel to learn more about the subjects mentioned above.

I have set the frequency range as 0 Hz to 10 GHz because of the stability simulation. Stability factors require simulation over a wide frequency band. The next frequency range is the ISM band low and high frequency, which is 2.4GHz and 2.5GHz, respectively. Finally, a single frequency is set at 2.45GHz. This is the center frequency of our band of interest.

Finally, we have to select a simulator before starting the simulation. To do that, click “simulator” and select FEM simulator. The rest of the settings are standard.

However, this is a large simulation and will take days on any system. One can simplify the simulation complexity. To do that, click on “edit advanced simulator setup”. Here, you can change generation to generation 2, mesh domain optimization to ON, and the refinement frequency to 2.5GHz, which is the high frequency of our band of interest. These setting changes reduce simulation time drastically. In my case, I’m willing to wait, so I didn’t do that.

After doing all the setup, Run needs to be clicked to begin the RFPro simulation.

1.9 Step 7: EM-circuit co-simulation

Upon completing the EM simulation, the EM simulation model is created and placed onto the ADS schematic, so EM-Circuit Co-Simulation can be done by clicking “Results” à”Generate Sub Circuit mode.”

As shown in Figure 1.29, we have built the circuit with our EM simulation model. I want to highlight that the same component values are used between the circuit and layout simulations except for the resistor R7. We have reduced the R7 value from 12.7 ohms to 6 ohms in order for the LNA to pass the gain specification. The same components value for both the circuit simulation and layout simulation is possible because we have minimized the parasitics.

Figure 1.29: Parasitic inductance formation in the PCB.

1.10 Step 8: Results and Analysis

The s-parameter performance of the circuit simulation is shown in Figure 1.30.  20dB gain was obtained across the band of interest, 2.4GHz to 2.5GHz. Isolation of -29dB is achieved in the band of the LNA operation. Input return loss is less than -9.5dB, whereas output return loss is less than -13.7 dB.

In conclusion, the LNA meets gain and reverses isolation and output return loss specifications, but Input return loss. Input return loss is failing by 0.5dB. However, we can live with this because the most critical parameters, such as gain and isolation, meet the spec.

Figure 1.30: LNA s-parameter simulation results

Figure 1.31 shows the Noise Figure and DC simulation. The excellent noise figure of 0.78dB was obtained across the band. A Collector current (I_ce) of 0.017mA is obtained, which is also the total current draw of the LNA.

Figure 1.32 shows the small signal stability analysis. Through the WS Probe, we have plotted the “Real Part of Driving Point Admittance” and “Bilateral (True Return Ratio) Loop Gain.” We also plotted µ_source & µ_load. The µ_source & µ_load > 1 shows the LNA is unconditionally stable. Moreover, the “Real Part of Driving Point Admittance” is more than zero, and the “Bilateral (True Return Ratio) Loop Gain” is less than 0 validates the mentioned conclusion.

Figure 1.31: Noise Figure and DC simulation results

Figure 1.32: LNA small signal stability analysis

Next, we will analyze the IP3 simulation data.

In the IP3 measurement, Two signals with an appropriate gap will be injected into the LNA, and a spectrum analyzer will monitor the output. In our case, we inject 2.449GHz and 2.451GHz together. The fundamental frequency is 2.45GHz, and the gap is 1MHz between the two mentioned signals. In the industry, sometimes this gap can be in kHz, depending upon the radio specification. The power level is -40dBm. The OIP3 can be calculated using this IP3out component in ADS. I have inserted two components because we have upper and lower-side OIP3 products.

The rest of the setup in the schematic is standard or similar compared to our previous schematic for the s-parameter and noise figure simulation. Figure 1.33 shows the OIP3 simulated values. OIP3 is more than 15dBm, which also meets our design specifications.

Figure 1.33: LNA Output OIP3 Simulation