Tutorial 1: Step-by-Step Guide to Designing a Low Noise Amplifier for the ISM Band (2400MHz To 2500MHz)
In this tutorial, we will learn the step-by-step guideline of a Low Noise Amplifier (LNA). For this tutorial, we will design an ISM band LNA for 2.4GHz to 2.5GHz applications. However, the technique presented here can be used to design LNA for any frequency band of interest.
Eight steps are involved in designing an LNA, which is given in Table 1.1. Firstly, a device will be selected. Secondly, the LNA impedances need to be obtained. Thirdly, impedance matching for the LNA should be done. The fourth step is the circuit design and simulation. As a fifth step, layout design should be done. Then Layout simulation should be conducted, followed by EM-circuit Co-simulation. Finally, simulation results will be analyzed. In this step, measurement and correlation between simulation and measurements are not included. Maybe in the future, we can include measurements and correlation analysis as well.
Table 1.1: Design Steps of a Low Noise Amplifier (LNA)
We will start by briefly introducing the LNA.
1.2 LNA Introduction
Let’s start our tutorial with the LNA introduction.
Figure 1.1 shows the basic RF radio system contains a baseband processor, up-conversion Mixer, down-conversion Mixer, Voltage Controlled Oscillator (VCO), Local Oscillator (LO) or Frequency Generating Unit (FGU), pre-driver, driver, final Power Amplifier (PA), coupler, power controller, antenna switch, harmonic filter, antenna, pre-selector filter, Low Noise Amplifier (LNA) and post-selector filter. Each radio component plays a unique and significant part in achieving the end goal of receiving and transmitting information wirelessly over a long distance.
The LNA is located at the receiver chain of the radio system. The receiver chain and LNA are shown in Figure 1.2. The signal received by the antenna will be routed to the receiver section by the antenna switch. The Preselector filter will filter out-of-band frequencies and route the received signal to the LNA. The LNA is responsible for amplifying weak received signals with the addition of minimal noise. Post-Selector Filter will further filter the received signal to be passed on to the downconverter mixer and then the baseband processor.
The LNA is also responsible for providing additional isolation from the Mixer to the antenna. Since LNA introduces noise to the receiver chain, it affects receiver sensitivity and Intermodulation distortion. The challenge of LNA designers is minimizing noise introduced by LNA while optioning appropriate gain and efficiency.
1.2.1 LNA Implementation
Two ways of implementing an LNA are Discrete and integrated Circuit Implementation. Each implementation has its advantages and disadvantages. Table 1.2 lists the characteristic of a Discrete LNA vs. an Integrated Circuit LNA, whereas Table 1.3 exhibits the characteristics of an Integrated LNA compared to Discrete LNA.
|Inexpensive implementation||Lower reliability compared to IC|
|Can be repaired if design not meeting goal during bench testing||Limited bandwidth compared to IC|
|Low transmission line loss compared to IC||Uncontrolled parasitics|
|Higher components Q||Large size|
|Wide variety of components / lumped elements||High assembly cost|
|Limited to low frequency|
|Small Size and Weight||High cost compared to PCB implementation in small quantities.|
|Broader bandwidth||No Tuning|
|Design Flexibility because we can design whatever value of lumped components we want.||Higher transmission line losses|
|Improved reliability||Undesired RF coupling|
|Good reproducibility||High Equipment cost|
|Lower cost in volume||Limited component values are available. Custom components can be designed but at a higher cost.|
|Very broad Frequency for MMIC|
Even though there are two ways of implementing LNA, both are relevant. The designer can choose one according to the product specification or application. For our application, we will be moving ahead with Discrete LNA implementation.
1.2.2 Cumulative Noise Figure by Friis’s Equation
Friis’s equation is an essential formula that enables us to calculate the receiver sensitivity. We can also calculate the IP3 and IP2 of a receiver chain. However, since we are focusing on LNA design only in this training, I will stop at the cumulative noise figure. Figure 1.3 shows the receiver chain. The numeric gain and the noise figure of each component on the receiver chain are below that.
The Friis’s Equation is given by Equation 1.1. The first term (F1) in the equation above is the most significant contributor to the cumulative noise figure because it’s not divided by gain. Due to this, it’s essential to minimize the noise figure of the 1st stage of the cascaded receiver system.
1.2.3 Type of Noise
In a receiver system, noise is the main obstacle. Both passive and active components generate noise. There are Six types of noise available.
184.108.40.206 Thermal noise
Thermal noise, also called Johnson–Nyquist noise, is unavoidable. Its generated by the random thermal motion of charge carriers or electrons inside an electrical conductor, which happens regardless of any applied voltage.
Thermal noise is approximately white, meaning its power spectral density is nearly equal throughout the frequency spectrum. The amplitude of the signal has almost a Gaussian probability density function. A communication system affected by thermal noise is often modeled as an additive white Gaussian noise (AWGN) channel.
220.127.116.11 Short noise
Short noise in electronic devices results from unavoidable random statistical fluctuations of the electric current when the charge carriers (such as electrons) traverse a gap. If electrons flow across a barrier, then they have discrete arrival times. Those discrete arrivals exhibit shot noise. Typically, the barrier in a diode is used. Shot noise is similar to the noise created by rain falling on a tin roof. The flow of rain may be relatively constant, but the individual raindrops arrive discretely.
The Schottky formula gives the root-mean-square value of the shot noise current in ;
Where I is the DC, q is the charge of an electron, and ΔB is the bandwidth in hertz.
Conductors and resistors typically do not exhibit shot noise because the electrons thermalize and move diffusively within the material; the electrons do not have discrete arrival times. Shot noise has been demonstrated in mesoscopic resistors when the size of the resistive element becomes shorter than the electron-phonon scattering length.
18.104.22.168 Flicker noise
Flicker noise, also known as 1/f noise, is a signal or process with a frequency spectrum that falls off steadily into the higher frequencies, with a pink spectrum. It occurs in almost all electronic devices and results from various effects, though it is always related to a direct current (DC).
22.214.171.124 Partition noise
Where current divides between two (or more) paths, noise occurs due to random fluctuations during this division. For this reason, a transistor will have more noise than the combined shot noise from its two PN junctions.
126.96.36.199 Burst noise
Burst noise consists of sudden step-like transitions between two or more discrete voltage or current levels, as high as several hundred microvolts, at random and unpredictable times. Each shift in offset voltage or current lasts for several milliseconds to seconds. It is also known as popcorn noise for the popping or crackling sounds it produces in audio circuits.
188.8.131.52 Transit-time noise
Sometimes, the time the electrons travel from emitter to collector in a transistor becomes comparable to the period the signal is amplified. In that case, at frequencies above VHF and beyond, the transit-time effect takes place, and the noise input impedance of the transistor decreases. From the frequency at which this effect becomes significant, it increases with frequency and quickly dominates other noise sources.
1.2.4 LNA Stage Specs vs. nonlinear Receiver Line UP/System Specs
Nonlinear Receiver line-up specifications are usually done in Keysight SystemVue. Nonlinear receiver Line-up specifications contain the entire receiver components, such as the antenna, pre-selector filter, Low Noise Amplifier (LNA), post-selector filter, and Mixer, and show the overall specification needed for the radio to operate well.
Keysight SystemVue simulates the input power to each stage, output power from each stage, Gain, Noise Figure, efficiency, Linearity, receiver sensitivity, third-order intercept point (IP3), and second-order intercept point (IP2). Nonlinear receiver line-up specifications need to be done for all the power modes that the radio support and consider the worst-case conditions such as lowest power and highest current drain.
1.2.5 LNA Parameters
These are the LNA parameters simulated using Keysight ADS.
Pin_RF – is RF Input power into the LNA.
S(2,1) – is LNA Small Signal Gain.
Noise Figure – Measures how much noise the LNA introduces into the system. It will affect the sensitivity.
OIP3 – Measures how linear the LNA is. It will affect IM performance.
S(1,1) and S(2,2) – is Input and Output Return Loss. It shows how well the Input and output matching is done.
S(1,2) – is Reverse Isolation. It shows how well LNA isolates the Input from the output.
Ice – is the DC drawn of the LNA
RFfreq– is the Frequency range of the LNA
muload, musource, Real Part of Driving Point Admittance, Bilateral (True Return Ratio) Loop Gain – How stable is the PA to variations in load VSWR, Temperature, voltage, and input power?
The stability issue happens when LNA oscillates similarly to an oscillator. The stability can be solved by avoiding signals from the output from coupling in-phase with the Input. Stability is checked in the design stage by simulating Stability factors such as µload and µsource.
We will also study WS Probe stability analysis. WS Probe has many stability analyses within. We will analyze the “Real Part of Driving Point Admittance” and “Bilateral (True Return Ratio) Loop Gain” in the WS Probe.
Common Stability fixes are Collector and Base bypass capacitor, RC-feedback (sacrifices gain at low frequencies for stability), Input resistive loading (sacrifices noise figure), Output resistive loading (sacrifices gain, power, IIP3), and Emitter feedback resistor (sacrifices gain at high frequencies).
1.3 Step 1: Device Selection
The most important step but often undermined. The device must be selected based on the LNA stage specification derived from the transmitter line-up or system specifications.
1.3.1 Design Specification
To select a device, we need to have design requirements for the LNA. The LNA design requirement is derived from the transmitter line-up specification. Generally, a technical manager or team leader will handle transmitter line-up specifications, and engineers will be given specifications to design the LNA accordingly.
These are the specifications we would like to focus on for this tutorial. The frequency range of the LNA is 2.4GHz to 2.5GHz, and the gain is around 20dB. The design should be unconditionally stable across a wide frequency range. Input and output return loss should be less than -10dB. The noise figure should be less than 1dB, and OIP3 should be more than 15dBm.
|Design Parameters||Design Specification|
|Frequency range||2.4GHz – 2.5GHz|
|Stability||µsource & µload 1,|
dB(LGC), dB(LGB) 0
|Input Return Loss (S11)||-10dB|
|Output Return Loss (S22)||-10dB|
1.3.2 Understanding Device Technology
Device technology needs to be understood to select a suitable device effectively. The selection of a device is the most crucial step. The device must be chosen based on the LNA stage specification.
Device technology must be understood to effectively select a suitable device for our Driver LNA. Please take a look at the graph attached here. This graph is taken from the analog devices website. As you can see, device technology varies as we vary the power level and the frequency. For low-power applications of less than 1W, SiGe is most suitable. GaAs will be the right technology for power applications between 1W to 6W and frequency range up to 100GHz.
For power above 6W, Silicon LDMOS, GaN/Si, and GaN/SiC are suitable. For high-power and low-frequency applications, Silicon LDMOS is most suitable. For high-power and mid-frequency applications, GaN/Si devices will serve better. For high-power and high-frequency applications, GaN/SiC devices are the best.
Besides power and frequency, the supply voltage also dictates device selection because the device supply voltage varies from 2V to 50V.
To learn more about device technology, please go to the link below.
1.3.3 Parameters of selected devices
NXP’s BFU730F is identified as the right candidate for the LNA. BFU730F is NPN silicon-germanium BJT.
These are the parameters of the selected device from the datasheet. (Table 1.6). From these parameters, we know that BFU730F will be able to meet our LNA design specifications.
|Noise Figure (NF)||0.55dB|
|Transition Frequency (fT)||55 GHz|
|Ccbs (collector base capacitance)||55fF|
1.3.4 Device Model Selection
The BFU730F supplier NXP has provided two device models: MEX and SPICE. There are two ways to select a suitable or most accurate device model. Those are comparing the impedance with the s-parameter data and the IV curve with the datasheet.
ADS template simulation is used to plot the IV curve. It can be launched by clicking DesignGuide à Amplifier à DC and Bias Point Simulations and à BJT I-V Curves, Class A Power, Eff., Load, Gm vs. Bias.
184.108.40.206 Compare the impedance with the s-parameters
Another way to select a device model is by comparing the simulation results of ADS models. Figure 1.5 shows the impedance simulation setup of s-parameter data.
Figure 1.6 shows the MEX model impedance simulation setup. Figure 1.7 shows the correlation between MEX model simulation and S-parameter data simulation. The MEX model correlates well with s-parameter data.
Figure 1.9 shows the SPICE model impedance simulation setup. Figure 1.10 shows the correlation between the SPICE model simulation and S-parameter data simulation. The SPICE model correlates well with s-parameter data.
The MEX model is proven as the most accurate model for BFU730F. All the simulations in the following steps will use the BFU730F MEX model.
220.127.116.11 Compare the IV curve with the datasheet
Apart from the above-mentioned method, the DC Curve (Ic vs. Vce) can be used to select the most accurate device model. The Ic vs. Vce from the datasheet can be compared with the Ic vs. Vce plot of the MEX and SPICE model to choose the model which closely matches the datasheet.
After comparing Figure 1.12 with 1.13 and 1.14, the MEX model is closely matched to the datasheet.
1.4 Step 2: Obtain the LNA impedances
The next step is to obtain the LNA input and output impedances. For PA, load-pull simulation is necessary because it’s a large signal circuit. However, we can live with S-parameter simulation for LNA because of the small signal characteristics.
The template for LNA impedance extraction simulation can be found under DesignGuide à Amplifier à S-parameter Simulations. The template’s name is “S-param., Noise Fig., Gain, Stability, Circles, and Group delay versus Frequency”, as shown in Figure 1.15. S-parameter data or the MEX model can be used for the impedance simulation. I have used the MEX model, as shown in Figure 1.16.
We built the biasing circuit, which gives appropriate collector-emitter voltage (Vce) and base current (Ib) according to the biasing condition of interest. The optimization setup shown on the left is done to obtain unconditional stability by optimizing RF choke, L3, and L4 and decoupling capacitors C10, C9, C11, and C12. Since these parameters are inadequate to provide unconditional stability to the LNA, we have used additional components, R7. The resistor R7 is used at the output match to trade gain for stability. With R7, we have obtained unconditional stability over a wide range of frequencies.
In this Figure 1.17, we can move this RF Frequency selector marker to an appropriate frequency point, and all the boxes below show the parameters for the frequency point. We have set the frequency point at the center of our band of interest, 2.45GHz. The four boxes below the RF frequency selector show the s-parameter data.
We have two options here. The 1st one is to do matching for gain. If we select this option, we need to use these impedances to do impedance matching for our LNA, and we will get the highest gain of 22 dB.
The 2nd option is to do impedance matching for the noise figure. If we do impedance matching for our LNA using the impedances shown in the box below, we will achieve the best possible noise figure of 0.69dB. The gain is also more than 20dB, as shown in Figure 1.17. Since it will be able to meet both noise figure and gain specification, we will choose to match for noise figure, and impedances will follow as in this box.
1.5 Step 3: Impedance matching
After obtaining the impedances, we have to match the input and output impedance with 50 ohms. Impedance matching is done from LNA input and output impedance to 50 ohms. The impedance we obtained from the previous simulation is the complex conjugate LNA impedance. Its shown in figure 1.18 as Zi* and Zo*. Due to this, we need to reverse the sign of the imaginary part of these impedances to get the actual LNA impedances.
Zo* – complex conjugate of output impedance
Zi* – complex conjugate of input impedance
Zo – Transistor output impedance
Zi – Transistor input impedance
Figure 1.19 shows the output impedance matching, whereas Figure 1.20 shows the input impedance matching of the LNA. Impedance matching is done using the Smith chart utility.
The next step is to do impedance matching. ADS has a brilliant impedance-matching tool called the Smith chart utility. We will be using this tool to do impedance matching.
The 1st step is to make sure the frequency is set to the center frequency of our band of interest and the characteristic impedance is set to 50 ohms. The next step is to insert the Q circle value. For our frequency band of interest, the calculated Q circle value is 8.
Next, we have to match the LNA output impedance to 50 ohms.
Impedance matching is accomplished for load and source impedance.
1.6 Step 4: Circuit Simulation
The next step is circuit simulation. Before we simulate, we need to build the circuit. Our LNA circuit is shown in Figure 1.21. The matching component values obtained from step 3 will be used in the schematic here. On top of that, the LNA circuit also contains biasing circuit. The biasing circuit provides the required collector-emitter voltage (Vce) and base-emitter current (Ibe). We also have decoupling capacitors to filter out noise in the DC path. RF Chokes will block the RF from entering the DC path. I have incorporated DC-blocking capacitors in the Input and output matching components to block the DC from entering the RF path. All these components are shown in Figure 1.21.
Let’s move on to check our circuit simulation results. I create this data display server template. You can create a custom template like this and copy and paste it easily to recreate them, which saves a lot of time.
The s-parameter performance of the circuit simulation is shown in Figure 1.22. The LNA meets all the specifications, including gain and isolation and input and output return loss. The gain is more than 20dB which is excellent. The isolation is -29dB. The input return loss is less than -18dB, and the output return loss is less than -14.9 dB.
Figure 1.23 shows Noise Figure and DC simulation. The excellent noise figure of 0.92dB to 0.95dB was obtained across the 2.4GHz to 2.5GHz frequency range. The Collector current (Ice) of 0.017mA is obtained, which is also the total current draw of the LNA. The base current (Ibe) is very small and negligible, but ADS allows you to plot this as well.
Figure 1.24 shows the small signal stability analysis. Through the WS Probe, we have plotted the “Real Part of Driving Point Admittance” and “Bilateral (True Return Ratio) Loop Gain”. We also plotted µsource & µload. The µsource & µload > 1 across 1kHz to 20GHz shows the LNA is unconditionally stable. Moreover, the “Real Part of Driving Point Admittance” is more than zero, and the “Bilateral (True Return Ratio) Loop Gain” is less than 0 validates the mentioned conclusion.
Figure 1.25 shows the LNA IP3 measurement setup. Two signals with an appropriate gap will be injected into our DUT or LNA, and the output will be monitored by a spectrum analyzer. In our case, we are injecting 2.449GHz and 2.451GHz together, and the fundamental frequency is 2.45GHz and a gap of 1MHz. In the industry, sometimes this gap can be in kHz, depending upon the radio specification. The power level is -40dBm. The OIP3 can be calculated using this IP3out component in ADS. I have inserted two components because we have upper and lower-side OIP3 products.
We will do an IP3 simulation with the EM simulation model later.
For circuit simulation, we have met all the design goals set for the s-parameter, noise figure, and stability simulations.
1.7 Step 5: Layout Design
LNA layout must be carefully designed to minimize parasitic capacitance and parasitic inductance. The layout causes parasitic capacitance and parasitic inductance. As you already know, parasitic capacitance and inductance are unwanted elements due to the nature of the PCB.
Let’s understand what causes parasitic capacitance. Figure 1.26 shows parasitic capacitance formation in a PCB. In case one, the electric field between the traces on layer one forms parasitic capacitance. In other words, the electric field created between these M2 traces in blue causes parasitic capacitance.
In case two, the electric field between a trace on layer one and metal on the neighboring layers forms parasitic capacitance. for example, the electric field formed between M2, M3, and M1 will also create parasitic capacitance.
Now let’s understand how parasitic inductance is formed. The magnetic field between two ends of a trace forms parasitic inductance, as shown in Figure 1.3. long traces will have huge parasitics inductance and wise versa.
RF engineers need to be aware of the parasitic capacitance and inductance and learn to minimize or control parasitics in the layout to avoid unwanted issues such as LNA low gain or stability issues. Layout design needs to be done carefully with complete awareness of parasitics. PCB layout is designed to minimize parasitic capacitance and parasitic inductance.
1.8 Step 6: Layout Simulation
The sixth step is to do a layout simulation. Layout simulation needs to be done after designing the layout to ensure layout parasitics are not degrading the circuit performances such as gain, noise figure, stability, IP3, etc. Our youtube videos have a step-by-step guide on importing the layout into Keysight ADS in ODB++ format, setup the EM simulation, and Running it. Please check the videos on Innowave’s youtube channel to learn more about the subjects mentioned above.
I have set the frequency range as 0 Hz to 10 GHz because of the stability simulation. Stability factors require simulation over a wide frequency band. The next frequency range is the ISM band low and high frequency, which is 2.4GHz and 2.5GHz, respectively. Finally, a single frequency is set at 2.45GHz. This is the center frequency of our band of interest.
Finally, we have to select a simulator before starting the simulation. To do that, click “simulator” and select FEM simulator. The rest of the settings are standard.
However, this is a large simulation and will take days on any system. One can simplify the simulation complexity. To do that, click on “edit advanced simulator setup”. Here, you can change generation to generation 2, mesh domain optimization to ON, and the refinement frequency to 2.5GHz, which is the high frequency of our band of interest. These setting changes reduce simulation time drastically. In my case, I’m willing to wait, so I didn’t do that.
After doing all the setup, Run needs to be clicked to begin the RFPro simulation.
1.9 Step 7: EM-circuit co-simulation
Upon completing the EM simulation, the EM simulation model is created and placed onto the ADS schematic, so EM-Circuit Co-Simulation can be done by clicking “Results” à”Generate Sub Circuit mode.”
As shown in Figure 1.29, we have built the circuit with our EM simulation model. I want to highlight that the same component values are used between the circuit and layout simulations except for the resistor R7. We have reduced the R7 value from 12.7 ohms to 6 ohms in order for the LNA to pass the gain specification. The same components value for both the circuit simulation and layout simulation is possible because we have minimized the parasitics.
1.10 Step 8: Results and Analysis
The s-parameter performance of the circuit simulation is shown in Figure 1.30. 20dB gain was obtained across the band of interest, 2.4GHz to 2.5GHz. Isolation of -29dB is achieved in the band of the LNA operation. Input return loss is less than -9.5dB, whereas output return loss is less than -13.7 dB.
In conclusion, the LNA meets gain and reverses isolation and output return loss specifications, but Input return loss. Input return loss is failing by 0.5dB. However, we can live with this because the most critical parameters, such as gain and isolation, meet the spec.
Figure 1.31 shows the Noise Figure and DC simulation. The excellent noise figure of 0.78dB was obtained across the band. A Collector current (Ice) of 0.017mA is obtained, which is also the total current draw of the LNA.
Figure 1.32 shows the small signal stability analysis. Through the WS Probe, we have plotted the “Real Part of Driving Point Admittance” and “Bilateral (True Return Ratio) Loop Gain.” We also plotted µsource & µload. The µsource & µload > 1 shows the LNA is unconditionally stable. Moreover, the “Real Part of Driving Point Admittance” is more than zero, and the “Bilateral (True Return Ratio) Loop Gain” is less than 0 validates the mentioned conclusion.
Next, we will analyze the IP3 simulation data.
In the IP3 measurement, Two signals with an appropriate gap will be injected into the LNA, and a spectrum analyzer will monitor the output. In our case, we inject 2.449GHz and 2.451GHz together. The fundamental frequency is 2.45GHz, and the gap is 1MHz between the two mentioned signals. In the industry, sometimes this gap can be in kHz, depending upon the radio specification. The power level is -40dBm. The OIP3 can be calculated using this IP3out component in ADS. I have inserted two components because we have upper and lower-side OIP3 products.
The rest of the setup in the schematic is standard or similar compared to our previous schematic for the s-parameter and noise figure simulation. Figure 1.33 shows the OIP3 simulated values. OIP3 is more than 15dBm, which also meets our design specifications.
|Design Parameters||Design Specification||Simulated Results|
|Frequency range||2.4GHz – 2.5GHz||2.4GHz – 2.5GHz|
|Stability||µsource & µload 1,|
dB(LGC), dB(LGB) 0
|µsource & µload 1,|
dB(LGC), dB(LGB) 0
|Input Return Loss (S11)||-10dB||-9.5dB to -10.2dB|
|Output Return Loss (S22)||-10dB||-13.7dB|
|Noise Figure||1dB||0.779dB to 0.788dB|
|OIP3||15 dBm||15 to 15.3|
This table summarizes the LNA performance and compares it to the design specifications. LNA meets design goals for gain, stability, output return loss, noise figure, and OIP3. As mentioned earlier, input return loss is marginal, but we assume it should be fine.
The video links of the LNA design Tutorial is given below.