Tutorial 2: Step-by-Step Guide to Designing Reactively Matched Power Amplifier for the ISM Band (2400MHz to 2500MHz)
In this tutorial, we will learn the complete design guide of reactively matched power amplifiers from scratch. For this tutorial, we will design a power amplifier for ISM band or 2.4GHz to 2.5GHz applications.
Table 2.1 shows the steps required to design a power amplifier. We will begin the topic by presenting the Power Amplifier introduction. Pay careful attention to the following steps because those are steps required to design a power amplifier. A device must be selected based on the specification. Secondly, DC analysis must be performed using the Loadline theory. Thirdly, Source and Loadpull need to be performed. The fourth step is Impedance matching, followed by Circuit simulation. The sixth step is Layout design and simulation, followed by EM-Circuit Co-Simulation. Finally, we will review and Analyze the Results. The measurement of the fabricated design will not be covered in this tutorial.
Table 2.1: PA Design Steps
Figure 2.1 shows the basic RF and microwave radio architecture. A basic RF radio system contains a baseband processor, up-conversion mixer, down-conversion mixer, Voltage Controlled Oscillator (VCO), Local Oscillator (LO) or Frequency Generating Unit (FGU), pre-driver, driver, final Power Amplifier (PA), coupler, power controller, antenna switch, harmonic filter, antenna, pre-selector filter, Low Noise Amplifier (LNA) and post-selector filter. Each radio component plays a unique and significant part in achieving the end goal of receiving and transmitting information wirelessly over a long distance.
RF amplifier is one of the most critical sub-systems of an RF radio system. The signal generated by the Voltage Controlled Oscillator (VCO) or Local Oscillator (LO) will be passed on to the RF amplifier for amplification. A well-designed RF amplifier amplifies the frequency band of interest with adequate efficiency and linearity.
Let’s look at the Transmitter lineup shown in Figure 2.2 below. It contains VCO, pre-driver, Driver and Final Power Amplifier, Antenna switch, and Harmonic Filter. Note that the Power Amplifier, including the Pre-driver, Driver, and Final Power Amplifier as a Single Power Amplifier, cannot amplify the signal to an adequate power level for signal transmission. Usually, Radios will be 1Watts to up 100Watts depending on the application. The PA configuration and topology may vary according to the operating power level.
2.1.1 Possible PA Configuration
Figure 2.3 shows commonly used PA configurations. The first configuration is a two-stage power amplifier with only a driver PA and a final PA. The second one has a Driver PA and a Final PA. The final PA configuration can be either power combiner PA or push-pull PA. The third configuration is the most used configuration for high-power radios. This configuration has three stages which are pre-driver, Driver, and PA.
2.1.2 PA Implementation Technique
Next, we will cover two PA implementation techniques, Discrete PA vs. integrated circuit PA. In the discrete PA design approach, designers will select a device that will either be BJT or FET and design the rest of the circuit which goes into it. Integrated Circuit PA is PA that has been designed in an IC with 50ohm Input and output connections. The Designers have to implement the PA onto their radio.
Table 2.2 shows the comparison between discrete and Integrated Circuit Implementation. Discrete PA provides pre-amplification for either the driver stage, final stage PA or harmonic filter. It also provides isolation between the final stage and VCO/VCO buffer. Discrete PA also provides power control with the goal of having approximately linear gain vs. Pin in the tuning range. Discrete PA is also lower cost but has high parts count and requires large PCB space.
Integrated Circuit (IC) PA has the same function as discrete PA but is integrated within multi-stage PA. The design is less flexible, and typically, input and output are internally matched to 50-ohms. The power control scheme varies with module design, e.g., self-bias, external Vctrl (control voltage), or On/Off. IC also has lower parts courts but also has a short part lifetime.
We are using discrete PA implementation for this tutorial.
|Discrete PA||Integrated PA|
|Flexibility to design changes||Lower parts count|
|Input usually internally matched to 50 ohm|
|High parts count||Not flexible to design changes|
|PCB space||Shorter part lifetime|
2.1.3 Power Calculation
PA is delivering power, so we need to know the power calculation. Power in dBm equals:
P[dBm] = 10 log ( P[Watt]/1mW)
Power in Watts equals:
P[Watts] = 10(P[dBm]/10)/1000
3dB up in dBm equals double the watts. Same way, 3dB down in dBm equals half the watts.
30 dBm = 1W
33 dBm = 2W
36 dBm = 4W
27 dBm = 0.5W
2.1.4 PA Stage Specs and Transmitter Line UP/System Specs
Table 2.3 shows the transmitter lineup specification or system specification. As you can see, the input power to each stage, output power from each stage, Transmit current, and some other parameters are calculated in this spreadsheet. Designers derive the specification for each power amplifier stage from this transmitter lineup specification. This transmitter lineup specification shows the overall specification needed for the transmitter to operate well. Usually, the project head of the company will derive this transmitter lineup specification or system specification.
Table 2.3: Transmitter Lineup Specification or System Specification
Transmitter lineup calculations are usually done in an Excel spreadsheet, as shown in Table 2.3. It contains the entire transmitter components such as pre-driver, driver, PA, antenna switch, harmonic filter, and antenna. This spreadsheet calculates the input power to each stage, output power from each stage, transmit current, PAE, Drain efficiency, etc. System specs need to be done for all the power modes that the radio support and consider the worst-case conditions, such as lowest power and highest current drain.
Nonlinear transmitter lineup specification is done using Keysight SystemVue. Nonlinear transmitter Lineup specification contains the entire transmitter components such as pre-driver, driver, final PA, antenna switch, harmonic filter, and antenna. This nonlinear transmitter lineup specification shows the overall specification needed for the radio to operate well. The specification for each PA stage is derived from this nonlinear transmitter lineup specification. In Keysight SystemVue, we can include the input power to each stage, output power from each stage, gain, P1dB, PAE, harmonics, and many other parameters for the nonlinear transmitter lineup specification. Keysight SystemVue simulates the input power to each stage, output power from each stage, gain, P1dB, PAE, Drain efficiency, etc. harmonics.
Nonlinear transmitter lineup specification needs to be done for all the radio-supported power modes and should consider the worst-case conditions such as lowest power and highest current drain.
There are three main classes of operation available for PA. The conduction angle defines these amplifier classes. The transistor biased ON as a function of input swing. We will look into classes of operation for our selected device, BFQ790.
2.1.5 Classes of Operation
Class A operation means the PA is always ON, and the conduction angle is 360 degrees. The theoretical efficiency is around 50%. This class exhibits the highest linearity and gain. The efficiency of this class is the lowest because it’s always ON. Class A PA will be prone to an overheating problem, so a good heat sink design is inevitable.
Figure 2.4 shows the class A operation in graphical form for BFQ790, Ic vs. Vce. This is the output current vs. output voltage for the device we selected, BFQ790. The black color line is the drawn loadline, and for class A operation, the Q should be in the middle region of the loadline so the RF voltage swing will be unclipped.
Class B operations mean the PA is only ON for half-swing, and the conduction angle is 180 degrees. The theoretical efficiency is around 78%. Class B is less linear and has less gain compared to class A. Class B also exhibits less heating problems compared to Class A. One of the examples of Class B is the push-pull amplifier design, where each device conducts 180 degrees of the output waveform. Class B is prone to cross-over distortion problems.
The class B graphical representation is given in Figure 2.5. Ic vs. Vce is shown for the device we selected, BFQ790. The black color line is the drawn loadline, and for class B operation, the Q should be at the Vceo region of the loadline so the RF voltage swing will be clipped into half.
Class AB is the combination of classes A & B. The conduction angle of class AB is between 180 degrees and 360 degrees. The theoretical efficiency of class AB is 50 to 60%. Figure 2.6 represents class AB operations graphically. The Ic vs. Vce is shown for the device we selected, BFQ790. The black color line is the drawn loadline, and for class AB operation, the Q should be placed between classes A and B.
Class C has a conduction angle of less than 180 degrees, generally around 90 degrees. The highest theoretical efficiency we can achieve is around 80%. This class has the poorest linearity and gain compared to the rest of the classes. Class C also suffers heavy distortion. Similar to class B, class C also suffers cross-over distortion problems.
There are other classes of operations, such as D, E, and F. In these classes of operation, the device is intentionally driven into saturation using a square wave. This purposely avoids the linear region, operating the device only as a switch. Due to this, class D, E, and F amplifiers are often called switched-mode amplifiers. ON/OFF nonlinear switching makes conduction angle=0 and has theoretically 100% efficiency.
2.1.6 Important PA Parameters
The important PA parameters that a PA designer needs to know are given in the table.
|Pin_RF||RF Input power into a stage|
|Pin_dc||DC power consumption with RF input signal & amplification|
|Pout_RF||RF output power available to the next stage|
|Ls_Gain_dB||Large Signal Gain = Pout_RF – Pin_RF|
|P1dB||1 dB compression power (linearity)|
|P3dB||3 dB compression power (linearity)|
|Deff||Drain efficiency = Pout_RF/Pin_dc|
|PAE||Power Added Efficiency = (Pout_RF – Pin_RF)/Pin_dc|
|Ice||DC current drawn of the PA|
|RFfreq||Frequency range of the Power Amplifier|
|µload, µsource, Real Part of Driving Point Admittance, Bilateral (True Return Ratio) Loop Gain||How stable is the PA to variations in load VSWR, Temperature and voltage.|
A stability issue happens when PA oscillates similarly to an oscillator. Stability can be solved by avoiding signals from the output from coupling in-phase with the input. Stability is checked in the design stage by simulating Stability factors such as µload and µsource.
We will also study WS Probe stability analysis. WS Probe has many stability analysis within. We will analyze “Real Part of Driving Point Admittance” and “Bilateral (True Return Ratio) Loop Gain” in the WS Probe.
Common Stability fixes are RC-feedback, Collector/Drain bypass capacitor, and Base/Gate bypass capacitor.
An example of a stability issue is given here. If your PA has a stability issue, the spectrum analyzer output in a 100Hz span will look like this. Instead of amplifying the signal, the PA is oscillating.
2.2 Step 1: Device Selection
The first step of PA design is device selection. To select a device, we need to have a design requirement for the PA. As I explained before, the PA design requirement is derived from the transmitter line-up specification. Generally, a technical manager or team leader will handle transmitter lineup specifications, and engineers will be given specifications so they can design the PA accordingly.
2.2.1 Design Requirement of RF PA
For this tutorial, the specification in Table 2.5 is what we would like to focus on. The frequency range of the PA is 2.4GHz to 2.5GHz. The Input power is 14.5dBm. The maximum output power is 27dBm. 1 dB compression power or P1dB is 26dBm. The gain at 1 dB compression power is 13 dB. Drain efficiency should be around 40%. The design should be stable across a wide frequency range. Input and output return loss should be less than -10 dB. The PA we will design in this tutorial is a Driver PA.
|Design Parameters||Design Specification|
|Frequency range||2.4GHz – 2.5GHz|
|1dB Compression Power (P1dB)||26dBm|
|Stability||µsource , µload > 1|
|Input Return Loss (S11)||< -10dB|
|Output Return Loss (S22)||< -10dB|
|Where does the PA fit in the transmitter lineup?||Driver PA|
The selection of a device is the most important step but is often undermined in training. The device needs to be selected based on the PA stage specification derived from the transmitter lineup specification or the system specification.
2.2.2 Device Technology
Device technology must be understood to select a suitable device for our Driver PA effectively.
Figure 2.8 is taken from the analog devices website given above. As you can see, device technology varies as we vary the power level and the frequency. For low-power applications of less than 1W, SiGe is available to serve. For power applications between 1W to 6W and frequency range up to 100GHz, GaAs will be the suitable technology.
For power above 6W, Silicon LDMOS, GaN/Si, and GaN/SiC are suitable. For high-power and low-frequency applications, Silicon LDMOS is more suitable. For high-power and mid-frequency applications, GaN/Si devices will serve better. For high-power and high-frequency applications, GaN/SiC devices are the best.
Other than power and frequency, the supply voltage also dictates device selection because the supply voltage for devices varies from 2V to 50V. To learn more about device technology, please go to the link given above.
Figure 2.9 shows the parameters of the selected Device.
|Frequency||400MHz to 3500MHz|
2.2.3 Simulation Model Selection
In some cases, the device manufacturer will provide multiple simulation models. We can select the right model based on their description. Another way of choosing a suitable simulation model is to compare Ic Vs. Vce of the simulation model with Ic Vs. Vce in the datasheet. We should select a model that closely matches the datasheet’s Ic versus Vce plot.
To launch the I-V curve simulation template, go to “design guide” –>”Amplifier,” –>” DC and Bias Point Simulations,” –>”BJT I-V Curves..”. We have to modify the template to suit our simulation by changing the bias voltages and current and replacing our transistor.
Let’s simulate and check the data display. This is the Ic vs. Vce plot. I have compared the datasheet Ic vs. Vce in Figure 2.10 and simulated Ic vs. Vce in Figure 2.11. Good collaboration is obtained between the datasheet and simulation. Since Infineon only has a single-device model for this transistor, we have no choice other than to use this model. This method might be useful if the supplier provides multiple device models.
After an extensive search, BFQ790 is identified as the right candidate for drive PA of our design. Every design step from here onwards will use BFQ790.
2.3 Step 2: Dc Analysis and Loadline Theory
Step 2 of the PA design process is DC analysis and loadline theory. Loadline theory states that the power supply voltage and the maximum current of the transistor determine the maximum power a given transistor can deliver. In other words, loadline means maximum available power. The actual load will not be pure resistance and will always have some reactance. Voltage swinging close to Vknee will introduce distortion, which results in high harmonics.
Figure 2.12 shows a portion of the datasheet. In order to draw the loadline, we need Vceo, which is the maximum collector-emitter voltage, and the maximum DC collector current, which can only be obtained from the datasheet.
Next are the classes of operation simulation. I have used the ADS cell and data display server created by Matt Ozalas simulation for this simulation. You can get this template by searching a video titled “How to Design an RF Power Amplifier: Class A, AB, and B” on youtube. The loadline is drawn from the maximum collector-emitter voltage and the maximum DC collector current from Figure 2.12. You have to manually adjust the loadline to the correct position (maximum collector-emitter voltage and the maximum DC collector current) so the rest of the parameters will appear correctly.
Figure 2.13 shows the class A configuration. We know its class A is thru the conduction angle. Conduction angle 360 means it’s class A. We can also monitor the RF ideal voltage and ideal current swing, which is unclipped here. We should also observe the Maximum output power, small-signal gain, large-signal gain, efficiency, and DC from this template.
Figure 2.14 shows the class B configuration. We know its class B is thru the conduction angle. Conduction angle 180 means class B. We can also monitor the ideal RF current swing, which is clipped by half. We should also observe this template’s Maximum output power, small-signal gain, large-signal gain, efficiency, and DC.
Figure 2.15 shows the class AB configuration. We know its class AB is through the conduction angle. Conduction angle between 180 to 360 means class AB. We can also monitor the ideal RF current swing, which is clipped.
Class AB operation is selected for this PA since its driver is PA. Class AB is selected because it has both the high gain characteristic of class A and the high-efficiency characteristic of class B. This step has fixed the bias voltage (Vbe) and Vce.
2.4 Step 3: Loadpull
Step 3 in the PA design is Loadpull. The Loadpull is a measurement that varies a transistor’s input and output impedance to plot contours for maximum power and efficiency (PAE). Designers can select an impedance according to the power and PAE they want
The Q-point Vbe and Vce will be used to bias BFQ790. The Loadpull system will fix source impedance and vary load impedance. After that, load impedance will be fixed, and source impedance will be varied. This process needs to be repeated at least 3 times to plot power and PAE contours accurately.
Loadpull also can be simulated using Keysight ADS. The accuracy of loadpull simulation depends upon the device model’s accuracy.
The example of the loadpull setup from Google is shown in Figure 2.16. It has a source tuner and the load tuner. The device will be mounted at the center and connected to the load and source tuner. Figure 2.16 will give you an idea of the loadpull setup.
In this tutorial, we will only do a loadpull simulation to extract the load and source impedances.
Figure 2.17 below shows the device’s input and output impedance from the datasheet. For source impedance, we can select impedance at 2.6GHz because it’s close enough to 2.5GHz.
We can see that only impedance at 900MHz is given for load impedance. However, we can use this impedance at the initial impedance and tune the impedance in the loadpull simulation.
Figure 2.18 shows the load-pull simulation setup. This is also a template simulation. To launch the template, go to DesignGuide –> Loadpull –> One-Tone Load Pull Simulations –> and click “Constant Available Source Power”.
After replacing the transistor in the schematic shown in Figure 2.18, we need to set the bias voltages correctly according to our needs and the datasheet. In setting the Vbe and Vce, usually, the datasheet will supersede the Loadline simulation done in step 2. This is because loadline simulation is just an estimation based on the device model, whereas the datasheet has measured device data. Due to this, designers are often comfortably biasing the device according to the datasheet recommendation rather than loadline simulation. You can then ask me why we need loadline simulation in the PA design steps. As PA designers, we need to understand how the loadline theory works, as it’s an integral part of PA design.
We also need to set the input power (Pavs_dBm), RF frequency (RF_Freq), load impedance (Z_load_center_Fund), and source impedance (Z_source_Fund). We set the load and source impedance according to the datasheet. We have to double-click on the loadpull instrument to see the internal settings. I have selected no to “specify_load_center_S,” which means I have chosen to work with impedances instead of the reflection coefficient. I have selected “sweep_rectangular_region” as no, which means; the impedance points will be circular with the value we set in “S_load_radius,” and the number of points follows “Num_Points.” I have tried to increase the number of points, but I ended up with an error, so it’s recommended to stick to the default number of points.
Figure 2.19 shows the simulated results of the schematic in Figure 2.18. The PA output power and PAE contours show that we have not obtained the optimum power and PAE contours. How do we know if we have optioned the optimum power or PAE contour? If we obtained the optimum contour, we would see a small circle in the middle of the Power and PAE contours. This small circle indicates peak power and peak PAE. The rest of the circles in the contour will be centered around this small circle. Otherwise, we must tune the impedances until we see a small circle at the center of both power and PAE contours. In this case, we have to tune the load impedance since the datasheet only has load impedance for 900MHz.
There is a lot of information given in Figure 2.19. The highlighted box on the left corner shows the summary of important information needed. It’s given in the Figure 2.20.
The first box shows impedance at maximum power. We can see the PAE and gain at maximum power as well here. The second box shows impedance at maximum PAE. We can see the output power and Gain here. The third box displays impedance and other parameters in the contour as we move marker 1. Fortunately for this transistor, both peak power and peak PAE contour overlap with each other. Due to this, it’s easy to select our impedance because, as you can see, the peak PAE and peak power load, and source impedances are the same.
In conclusion, the selected impedance for maximum power and maximum PAE are shown in Figures 2.19 and 2.20.
2.5 Step 4: Impedance Matching
Step 4 in designing a PA is impedance matching. Figure 2.21 shows the concept of impedance matching. The output and input impedance of a PA will be 50 W. An input and output matching will be between 50ohm impedance and the transistor. The loadpull simulation has given us BFQ790’s complex conjugate of output and input impedance.
Zo* – Complex conjugate of output impedance obtained from Loadpull
Zi* – Complex conjugate of input impedance obtained from Loadpull
Zo – Transistor output impedance
Zi – Transistor input impedance
Figure 2.20 shows the complex conjugate of input and output impedance obtained from the loadpull simulation. Impedance matching is done from PA impedance to 50 W.
Impedance matching is done using the ADS Smith chart utility. Here is the step-by-step guide on how to use the Smith chart utility to do impedance matching.
First, we need to set the matching frequency, which is 2.45GHz. Next, we need to set the Q circle value. For our case, it’s 8. And then, we set the load impedance as PA input impedance and source impedance as 50 W. Matching is done from the load impedance to the source impedance. The input matching designed using the Smith chart utility is shown in Figure 2.22.
Similarly, for output matching, first, we need to set the matching frequency at 2.45GHz. Next, we need to set the Q circle value. For our case, it’s 8 as well. And then, we set the load impedance as PA output impedance and source impedance as 50 W. Matching is done from the load impedance to the source impedance. The output matching designed using the Smith chart utility is shown in Figure 2.23.
Impedance matching is accomplished for load and source impedance obtained from the loadpull simulation.
2.6 Step 5: Circuit Simulation
Figure 2.24 shows a PA circuit. The PA circuit contains Biasing circuit, DC blocking capacitors, and input and output matchings.
The biasing circuit contains an RF choke, decoupling capacitors, and a resistive voltage divider.
The PA circuit in Figure 2.24 has been designed with our selected device, BFQ790. The schematic is built from scratch. The red color circle shows biasing circuitry. The biasing circuitry contains a resistive divider, decoupling capacitors, which are circled in green, and RF chokes, which are circled in light blue. Then we have input and output matching circuits which are circled in black. The matching circuits also contain DC-blocking capacitors.
Figure 2.25 shows the PA schematic simulation setup. Equations are used to calculate all the large signal parameters. Optimization of passive components is inevitable because of the nonlinearity of the passive components.
Figure 2.26 shows PA small signal simulation results. The small signal gain is from 15.4dB to 15.7dB across the band. The input and output return loss is -7.5dB to -10.7dB and -9.8dB to -14.5dB, respectively.
Figure 2.27 shows the PA large signal parameters. The output power of the PA varies from 28.4dBm to 27.6dBm. The large signal gain of the PA is 13.98dB to 13.1 dB. The PAE is 62.6% to 67.5%, whereas drain efficiency is 64.6% to 70.48%.
Figure 2.28 shows the PA small signal stability analysis. Mu_load and Mu_source show the PA is unstable after 7GHz. However, based on my experience, we need not fear this yet. Usually, high frequency, which is unstable during circuit simulation, will be stable in layout simulation.
The real part of driving point admittance is positive for both collector and base nodes [real(1/C.H0) & real(1/B.H0)], indicating the circuit is stable. Moreover, the bilateral true return ratio loop gain at collect and base [dB(LGC) & dB(LGB)] is less than zero, which means the circuit is stable. These are the stability analysis done via WS Probe. To know the details of these WS Probes and the stability analysis, please watch videos titled “How to design a stable high-frequency Amplifier” from Matt Ozalas on the Keysight design software youtube channel.
Figure 2.29 shows the large signal stability analysis of our PA. To do a large signal stability analysis, double-click on the Harmonic Balance (HB) simulation controller component. A popup will appear showing all the settings of the HB simulation controller. Under the small-signal tab, enable small signal, perform stability analysis, click apply, then OK.
Driving point admittance, real(1/C.H0)) & real(1/B.H0)) positive indicates the PA is stable. Bilateral loop gain, dB(LGC) & dB(LGB) less than zero indicate the PA is stable.
Figure 2.30 shows the P1dB (1 dB compression power) simulation template. P1dB is a measure of linearity.
Figure 2.31 shows the P1dB of 27.4dBm.
In summary, PA circuit simulation meets all the design goals.
2.7 Step 6: Layout Design and Simulation
2.7.1 PA Layout Design Guidelines
PA layout must be carefully designed to minimize parasitic capacitance and parasitic inductance.
Please refer to Figure 2.32 to understand parasitic capacitance formation in a PCB Layout. In case 1 electric field between the traces on layer 1 forms parasitic capacitance. In case 2, the electric field between a trace on layer 1 and metal on the neighboring layers forms parasitic capacitance.
The source for Figure 2.32 and the explanation: https://www.edn.com/decreasing-parasitic-capacitance-in-ic-layouts/
Please refer to Figure 2.33 to understand parasitic inductance formation in a PCB Layout. The magnetic field between two ends of a trace forms parasitic inductance, as shown in Figure 2.33.
2.7.2 PA Layout
Step 6 is layout design and simulation. The layout should be designed to minimize parasitic capacitance and inductance. I have designed the layout using Altium Designer in all our previous videos on YouTube. For the first time in this tutorial, I will be using Keysight ADS to design the layout for our PA. The layout design using ADS is much simpler than Altium because ADS has auto-layout generation from the schematic and has the function to multiply the vias easily.
I will give you a step-by-step guide to designing the layout using ADS. Figure 2.25 above is the starting point. We are going to change Figure 2.25 to Figure 2.36. To do that, first, delete all simulation controllers, goals optimization controllers, and measure equations (meas_eqn), current probes, terms, and WS Probes because those are redundant.
Secondly, we have to change lumped components in the schematic with the ideal lumped components with artwork or footprint. To do that quickly, select all the capacitors in the design, then click edit –> component –> swap component and click OK. A popup window will appear. Change the cell name from “C” to “C_pad1” and click swap. Do the same for inductors and resistors.
Thirdly, change the lumped component’s footprint according to the size of your intended components. As shown in Figure 2.34, for inductors, capacitors, and resistors, only 3 parameters are involved, pad’s width (W), pad’s length (S), and component’s length (L1). These parameters can be changed together. To do that, select all the components in the schematics, go to Edit –> Components –> Group Edit Parameter Value.. and change the Parameter Name to W, S, and L1 and change the Parameter Value according to the footprint of interest. We can even change the units using this step.
The fourth step is adding MLIN and MTEE between the lumped components and the transistor. To do that, create enough space between the components. Drag MLIN and MTEE into the schematics and change the W (width) and L (length) to the desired number. Please copy and paste them into the needed locations in the schematic. Clean up the schematic by deleting the lines shorting MLIN and MTEE. After completing this step, the schematic will look similar to Figure 2.35.
As a fifth step, click on Layout –> Generate/Update Layout and click Apply to generate the layout automatically.
The sixth step is to create the footprint of the transistor manually. Check the datasheet of the BFQ790 to know the exact shape of the footprint. On the ADS layout, click Create a Rectangle to create a rectangle following the shape of the BFQ790’s pads. Align the pads that you manually created. Verify the pad’s dimension by measuring it using an insert –> dimension line or Ruler.
The seventh step of creating a layout is creating planes on each layer. To create a plane, go to insert –> plane.. The clearance in the “create new plane” popup window is ground clearance around the traces and components. State the preferred number and draw a rectangle shape as desired. Change the layer name in the “create new plane” popup window to create ground planes on different layers.
The eighth step is to insert keep out as necessary. Go to insert –> Keep out to insert keep outs. Double click on the plane you insert keep out and click apply so the keep out will take effect.
The ninth step of layout creation is via insertion. To insert vias, go to insert –> via.. or circle. Before creating the via, make sure the right via layer is selected. We can also multiply via and paste it in one go. To do that, go to Edit –> Copy/Paste –> Step and Repeat… Set X Spacing, Y Spacing, Number of Rows, and Number of columns to easily multiply the vias and paste them to the desired location. Assign the vias to the right net.
The tenth step is to define a layer stack-up for the PCB board. The final step is to insert pins for all the component pads. Now the layout is ready for EM simulation and will look similar to Figure 2.35.
To watch the step-by-step process of designing the layout in ADS, please refer to the YouTube videos given in the link below or watch this video on our YouTube channel: https://www.youtube.com/watch?v=IxGO15cWxxI&t=421s
Launch RFPro by clicking Tools –> RFPro –> New or Open. RFPro, as shown in Figure 2.37, will appear.
Set the frequencies required in the Frequencies Tab, as shown in Figure 2.38.
Since it’s just a PA, saving fields are not required. So you can leave it as default, as shown in Figure 2.39. After clicking done, click Run to start the EM simulation.
2.8 Step 7: EM-Circuit Co-Simulation
After finishing the layout EM simulation in step 7, click “Generate sub-circuit Model”. A sub-circuit model, as shown in Figure 2.4, will be generated. Connect lumped components at the correct ports and place simulations controllers and equations similar to the schematic in Step 5. Due to layout parasitics, optimization is inevitable, so we need OPTIM and GOAL. Optimize the lumped components in the schematic shown in Figure 2.40 to meet all the goals.
Finally, we will look into EM circuit co-simulation and the results.
2.9 Step 8: Results and Analysis
The EM-Circuit Co-Simulation results are given in this section. The results are marginal for input and output return loss, which is acceptable because we have met all our important design specifications. Figure 2.41 shows an excellent gain of >14dB, and isolation of <-30dB is achieved for the PA.
Figure 2.42 shows the PA large signal parameters. The output power of the PA varies from 26.7dBm to 26.9dBm. The large signal gain of the PA is 12.2dB to 12.4 dB. The PAE is 35% to 36.9%, whereas drain efficiency is 36.7% to 39.1%.
Figure 2.43 shows the PA small signal stability analysis. Mu_load and Mu_source more than 1 show the PA is stable up to 10GHz.
The real part of driving point admittance is positive for both collector and base nodes [real(1/C.H0) & real(1/B.H0)], indicating the circuit is stable. Moreover, the bilateral true return ratio loop gain at collect and base [dB(LGC) & dB(LGB)] is less than zero, which means the circuit is stable. These are the stability analysis done via WS Probe.
Figure 2.44 shows the large signal stability analysis of our PA. Driving point admittance, real(1/C.H0)) & real(1/B.H0)) positive indicates the PA is stable. Bilateral loop gain, dB(LGC) & dB(LGB) less than zero indicate the PA is stable.
Figure 2.45 shows the P1dB (1 dB compression power) simulation template.
Figure 2.46 shows the P1dB of 26.6dBm.
In conclusion, the PA meets all the design requirements. The video links to the PA design Tutorials are given below.